sy100s834/sy100s834l ( 1, 2, 4) or ( 2, 4, 8) clock generation chip precision edge ? precision edge is a register ed trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com june 2011 m9999-060911 hbwhelp@micrel.com general description the sy100s834/l is low skew (1, 2, 4) or (2, 4, 8) clock generation chip designed explicitly for low skew clock generation applications. the internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. the devices can be driven by either a differential or single-ended ecl or, if positive power supplies are used, pecl input signal. in addition, by using the vbb output, a sinu soidal source can be ac- coupled into the device. if a single-ended input is to be used, the vbb output should be connected to the clk input and bypassed to ground via a 0.01f capacitor. the vbb output is designed to act as the switching reference for the input of the sy100s834/l under single-ended input conditions. as a result, this pin can only source/sink up to 0.5ma of current. the function select (fsel) input is used to determine what clock generation chip function is. when fsel input is low, sy100s834/l functions as a divide by 2, by 4 and by 8 clock generation chip. however, if fsel input is high, it functions as a divide by 1, by 2 and by 4 clock generation chip. this latter feature will increase the clock frequency by two folds. or (408) 955-1690 the common enable (en) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the low state. this avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. an internal runt pulse could lead to losing synchronization between the internal divider stages. the internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. upon start-up, the internal f lip-flops will attain a random state; the master reset (mr) input allows for the synchronization of the internal dividers, as well as for multiple sy100s834/ls in a system. data sheets and support documentation can be found on micrel?s web site at www.micrel.com . precision edge ? features ? 3.3v (sy100s834l) and 5v (sy100s834) power supply options ? 50ps output-to-output skew ? synchronous enable/disable ? master reset for synchronization ? internal 75k ? input pulldown resistors ? available in 16-pin soic package truth table clk en mr function z l l divide zz h l hold q 0 ? 2 x x h reset q 0 ? 2 notes: z = low-to-high transition. zz = high-to-low transition. f sel q 0 outputs q 1 outputs q 2 outputs l divide by 2 divide by 4 divide by 8 h divide by 1 divide by 2 divide by 4
micrel, inc. sy100s834/sy100s834l june 2011 2 m9999-060911 hbwhelp@micrel.com ordering information part number package type operating range package marking lead finish sy100s834zc z16-2 commercial sy100s834zc sn-pb sy100s834zctr (1) z16-2 commercial sy100s834zc sn-pb sy100s834lzc z16-2 commercial sy100s834lzc sn-pb sy100s834lzctr (1) z16-2 commercial sy100s834lzc sn-pb sy100834zi z16-2 industrial sy100s834zi sn-pb sy100834zitr (1) z16-2 industrial sy100s834zi sn-pb sy100834lzi z16-2 industrial sy100s834lzi sn-pb sy100834lzitr (1) z16-2 industrial sy100s834lzi sn-pb sy100834zg (2) z16-2 industrial sy100s834zg with pb-free bar-line indicator nipdau pb-free sy100834zgtr (1, 2) z16-2 industrial sy100s834zg with pb-free bar-line indicator nipdau pb-free sy100834lzg (2) z16-2 industrial sy100s834lzg with pb-free bar-line indicator nipdau pb-free SY100834LZGTR (1, 2) z16-2 industrial sy100s834lzg with pb-free bar-line indicator nipdau pb-free notes: 1. tape and reel. 2. pb-free package is recommended for new designs. pin configuration 16-pin soic (z16-2) or (408) 955-1690
micrel, inc. sy100s834/sy100s834l june 2011 3 m9999-060911 hbwhelp@micrel.com pin description pin name pin function clk differential clock inputs. f sel function select, single-sided ecl logic. en synchronous enable, single-sided ecl logic. mr master reset, single-sided ecl logic. v bb reference output. q0 differential 1 or 2 outputs. q1 differential 2 or 4 outputs. q2 differential 4 or 8 outputs. 3.3v pecl output dc electrical characteristics (1) v cc = 3.3v 10%; r l = 50 ? to v cc ? 2v; v ee = gnd. t a = ? 40 c t a = 0 c t a = + 25 c t a = + 85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit i ee power supply current ? ? 49 ? ? 49 ? ? 49 ? ? 54 ma v ch output high voltage 2.215 2.295 2.42 2.275 2.235 2.42 2.275 2.345 2.42 2.275 2.345 2.42 v v ol output low voltage 1.47 1.605 1.745 1.49 1.595 1.68 1.49 1.595 1.68 1.49 1.595 1.68 v v ih input high voltage 2.135 ? 2.42 2.135 ? 2.42 2.135 ? 2.42 2.135 ? 2.42 v v il input low voltage 1.49 ? 1.825 1.49 ? 1.825 1.49 ? 1.825 1.49 ? 1.825 v v bb output reference voltage 1.92 ? 2.04 1.92 ? 2.04 1.92 ? 2.04 1.92 ? 2.04 v v cmr common mode range (2) 2 ? 2.9 1.9 ? 2.9 1.9 ? 2.9 1.9 ? 2.9 v i ih input high current ? ? 150 ? ? 150 ? ? 150 ? ? 150 a i il input low current 0.5 ? ? 0.5 ? ? 0.5 ? ? 0.5 ? ? a notes: 1. these values are for v cc = 3.3v. level specifications will vary 1:1 with v cc . 2. the cmr range is referenced to the most positive side of t he differential input signal. norm al operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between v pp (min.) and 1v. the lower end of the cmr range varies 1:1 with v ee . note for pecl operation that the v cmr (min.) will be fixed at 3.3v ? iv cmr (min.)i. or (408) 955-1690
micrel, inc. sy100s834/sy100s834l june 2011 4 m9999-060911 hbwhelp@micrel.com or (408) 955-1690 5v pecl output dc el ectrical characteristics (2) v cc = 3.3v 10%; r l = 50 ? to v cc ? 2v; v ee = gnd. t a = ? 40 c t a = 0 c t a = + 25 c t a = + 85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit i ee power supply current ? ? 49 ? ? 49 ? ? 49 ? ? 54 ma v ch output high voltage 3.915 3.995 4.12 3.975 4.045 4.12 3.975 4.045 4.12 3.975 4.045 4.12 v v ol output low voltage 3.17 3.305 3.445 3.19 3.295 3.38 3.19 3.295 3.38 3.19 3.295 3.38 v v ih input high voltage 3.835 ? 4.12 3.835 ? 4.12 3.835 ? 4.12 3.835 ? 4.12 v v il input low voltage 3.19 ? 3.525 3.19 ? 3.525 3.19 ? 3.525 3.19 ? 3.525 v v bb output reference voltage 3.62 ? 3.74 3.62 ? 3.74 3.62 ? 3.74 3.62 ? 3.74 v v cmr common mode range (2) 2 ? 4.6 1.9 ? 4.6 1.9 ? 4.6 1.9 ? 4.6 v i ih input high current ? ? 150 ? ? 150 ? ? 150 ? ? 150 a i il input low current 0.5 ? ? 0.5 ? ? 0.5 ? ? 0.5 ? ? a notes: 1. these values are for v cc = 5v. level specifications will vary 1:1 with v cc . 2. the cmr range is referenced to the most positive side of t he differential input signal. norm al operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between v pp (min.) and 1v. the lower end of the cmr range varies 1:1 with v ee . note for pecl operation that the v cmr (min.) will be fixed at 3.3v ? iv cmr (min.)i.
micrel, inc. sy100s834/sy100s834l june 2011 5 m9999-060911 hbwhelp@micrel.com or (408) 955-1690 necl output dc electrical characteristics v cc = gnd; r l = 50 ? to v cc ? 2v; v ee = ? 3.0v to ? 5.5v. t a = ? 40 c t a = 0 c t a = + 25 c t a = + 85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit i ee power supply current ? ? 49 ? ? 49 ? ? 49 ? ? 54 ma v ch output high voltage ?1085 ?1005 ?880 ?1025 ?955 ?880 ?1025 ?955 ?880 ?1025 ?955 ?880 v v ol output low voltage ?1830 ?1695 ?1555 ?1830 ?1705 ?1620 ?1810 ?1705 ?1620 ?1810 ?1705 ?1620 v v ih input high voltage ?1165 ? ?880 ?1165 ? ?880 ?1165 ? ?880 ?1165 ? ?880 v v il input low voltage ?1810 ? ?1475 ?1810 ? ?1475 ?1810 ? ?1475 ?1810 ? ?1475 v v bb output reference voltage ?1.38 ? ?1.26 ?1.38 ? ?1.26 ?1.38 ? ?1.26 ?1.38 ? ?1.26 v v cmr common mode range (1) ?1.3 ? ?0.4 ?1.4 ? ?0.4 ?1.4 ? ?0.4 ?1.4 ? ?0.4 v i ih input high current ? ? 150 ? ? 150 ? ? 150 ? ? 150 a i il input low current 0.5 ? ? 0.5 ? ? 0.5 ? ? 0.5 ? ? a note: 1. the cmr range is referenced to the most positive side of t he differential input signal. norm al operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between v pp (min.) and 1v. the lower end of the cmr range varies 1:1 with v ee . the numbers in the spec table assume a nominal v ee = ? 3.3v. note for pecl operation, the v cmr (min.) will be fixed at 3.3v ? iv cmr (min.)i.
micrel, inc. sy100s834/sy100s834l june 2011 6 m9999-060911 hbwhelp@micrel.com ac electrical characteristics (1) v ee = v ee (min.) to v ee (max.); v cc = gnd. t a = ? 40 c t a = 0 c t a = + 25 c t a = + 85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit t plh propagation delay to output clk 960 1100 1200 960 1100 1200 960 1100 1200 960 1100 1200 ps t phl mr 650 800 1010 650 800 1010 650 800 1010 650 800 1010 ps t skew within-device skew (2) ? ? 50 ? ? 50 ? ? 50 ? ? 50 ps t s set-up time en 400 ? ? 400 ? ? 400 ? ? 400 ? ? ps t h hold time en 200 ? ? 200 ? ? 200 ? ? 200 ? ? ps v pp minimum input swing 250 ? ? 250 ? ? 250 ? ? 250 ? ? mv tr tf output rise/fall times q (20% ? 80%) 275 400 525 275 400 525 275 400 525 275 400 525 ps notes: 1. parametric values specified at: ? 5v power supply range, 100s834 series: ? 4.2v to ? 5.5v ? 3v power supply range, 100s834l series: ? 3.0v to ? 3.8v 2. within-device skew is specif ied for identical transition. or (408) 955-1690
micrel, inc. sy100s834/sy100s834l june 2011 7 m9999-060911 hbwhelp@micrel.com timing diagram the en signal will freeze the internal clocks to the flip-flops on the first falling edge of clk after its assertion. the internal div iders will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. the ou tputs will transition to their next states in the same manner, time, and relationship as they would have had the en signal not been asserted. or (408) 955-1690
micrel, inc. sy100s834/sy100s834l june 2011 8 m9999-060911 hbwhelp@micrel.com package information xx-pin package type (code) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or other wise, to any intellectual property rights is granted by this document. except as provided in micrel?s terms and conditions of sale for such products, mi crel assumes no liability whatsoever, and micrel disclaims any expre ss or implied warranty relating to the sale and/or use of micrel products including l iability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual p roperty right. micrel products are not designed or authorized for use as comp onents in life support appliances, devices or systems where malfu nction of a product reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are in tended for surgical impla into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significan t injury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devi ces or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. can nt ? 2006 micrel, incorporated. or (408) 955-1690
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